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ISL84467
Data Sheet July 17, 2007 FN6521.0
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch
The Intersil ISL84467 device is a low ON-resistance, low voltage, bidirectional, Quad SPDT (Dual DPDT) analog switch designed to operate from a single +1.65V to +4.5V supply. Targeted applications include battery powered equipment that benefit from low rON (0.39) and fast switching speeds (tON = 33ns, tOFF = 16ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. With a supply voltage of 4.2V and logic high voltage of 2.85V at both logic inputs, the part draws only 12A max of ICC current. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This part may be used to "mux-in" additional functionality while reducing ASIC design risk. The ISL84467 is offered in small form factor package, alleviating board space limitations. The ISL84467 consists of four SPDT switches. It is configured as a dual double-pole/double-throw (DPDT) device with two logic control inputs that control two SPDT switches each. The configuration can be used as a dual differential 2-to-1 multiplexer/demultiplexer.
TABLE 1. FEATURES AT A GLANCE ISL84467 Number of Switches SW 4.3V rON 4.3V tON/tOFF 3.0V rON 3.0V tON/tOFF 1.8V rON 1.8V tON/tOFF Package 4 Quad SPDT (Dual DPDT) 0.39 33ns/16ns 0.45 34ns/18ns 0.65 50ns/25ns 16 Ld 3x3 TQFN
Features
* ON-Resistance (rON) - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39 - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65 * rON Matching Between Channels . . . . . . . . . . . . . . . . . 0.05 * rON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.05 * Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . <0.68W * Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns * Break-Before-Make * 1.8V Logic Compatible (+3V supply) * Low ICC Current when VinH is not at the V+ Rail * Available in 16 Ld 3x3 TQFN * ESD HBM Rating - COM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV - All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Battery-Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL84467 Pinouts
(Note 1) ISL84467 (16 LD TQFN) TOP VIEW
COM4 IN3-4 NO4 NC3
Truth Table
LOGIC 0 1 NOTE: NC SW ON OFF NO SW OFF ON
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
12
10
11
9
NC4 V+ NO1 COM1
13
COM3 NO3 GND NC2
Pin Descriptions
PIN V+ GND IN FUNCTION System Power Supply Input (+1.65V to +4.5V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin
14
15
16
1
2
3
4
5
6
7
8
COM2
IN1-2
NO2
NC1
COM NO NC
NOTE: 1. Switches Shown for Logic "0" Input.
Ordering Information
PART NUMBER (Note) ISL84467IRTZ ISL84467IRTZ-T PART MARKING 67TZ 67TZ TEMP. RANGE (C) -40 to +85 -40 to +85 PACKAGE (Pb-Free) 16 Ld 3x3 TQFN 16 Ld 3x3 TQFN Tape and Reel PKG. DWG. # L16.3x3A L16.3x3A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V Input Voltages NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA ESD Rating: Human Body Model (COMX) . . . . . . . . . . . . . . . . . . . . . . . . .>9kV Human Body Model (NOX, NCX, INX, V+, GND) . . . . . . . . . .>6kV Machine Model (COMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . .>700V Machine Model (NOX, NCX, INX, V+, GND) . . . . . . . . . . . . .>300V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) TQFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 5, 8) TYP MAX (Notes 5, 8) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+ (See Figure 5) V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 7) V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+ (Note 6) V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V 25 Full
0 0.4 0.45 0.05 0.06 0.05 0.05 -70 -165 -70 -165
V+
V
rON Matching Between Channels, rON rON Flatness, rFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
70 165 70 165
nA nA nA nA
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 6)
25 Full 25 Full Full 25 25 25
33 38 16 21 3 248 65 -85
ns ns ns ns ns pC dB dB
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel)
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Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4), Unless Otherwise Specified. (Continued) TEST CONDITIONS f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 TEMP (C) 25 25 25 MIN (Notes 5, 8) TYP 0.008 38 102 MAX (Notes 5, 8) UNITS % pF pF
PARAMETER Total Harmonic Distortion
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = +4.5V, VIN = 0V or V+ Full 25 Full Positive Supply Current, I+ V+ = +4.2V, VIN = 2.85V 25 1.65 4.5 0.15 1.4 13 V A A A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 4.5V, VIN = 0V or V+ Full Full Full 1.6 -0.5 0.5 0.5 V V A
Electrical Specifications - 3.0V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 5, 8) TYP MAX (Notes 5, 8) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+ (See Figure 5) V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max rON (Note 7) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+ (Note 6) V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating 25 Full
0 0.55
V+ 0.75 0.85 0.08 0.19 0.22 0.07 0.15 0.15 1.1 30 1.5 45
V nA nA nA nA
rON Matching Between Channels, rON rON Flatness, rFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 1)
25 Full 25 Full Full 25 25 25
34 39 18 23 3 126 65 -85
ns ns ns ns ns pC dB dB
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF (See Figure 3) Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel) CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 4) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS (See Figure 6)
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ISL84467
Electrical Specifications - 3.0V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4), Unless Otherwise Specified. (Continued) TEST CONDITIONS f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600 f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) TEMP (C) 25 25 25 MIN (Notes 5, 8) TYP 0.012 38 102 MAX (Notes 5, 8) UNITS % pF pF
PARAMETER Total Harmonic Distortion NO or NC OFF Capacitance, COFF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 7) POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+
25 Full
0.021 0.72
A A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ Full Full Full 1.4 -0.5 0.5 0.5 V V A
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 5, 8) TYP MAX (Notes 5, 8) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON
Full V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+ (See Figure 5) 25 Full
0 0.7
V+ 0.9 0.95
V
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF (See Figure 1) 25 Full 25 Full Full 25 50 55 25 30 8 48 ns ns ns ns ns pC
Turn-OFF Time, tOFF
Break-Before-Make Time Delay, tD V+ = 2.0V, VNO or VNC = 1.0V, RL = 50, CL = 35pF (See Figure 3) Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2)
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 7. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4. 8. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. V+ = 2.0V, VIN = 0V or V+ Full Full Full 1.0 -0.5 0.5 0.4 V V A
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ISL84467 Test Circuits and Waveforms
V+ LOGIC INPUT 50% 0V tOFF SWITCH INPUT VNO 90% SWITCH OUTPUT 0V tON SWITCH INPUT VOUT 90% LOGIC INPUT NO or NC COM IN GND RL 50 CL 35pF VOUT V+ C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) ----------------------R L + r ON FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
SWITCH OUTPUT VOUT
DVOUT
RG
NO or NC
COM
VOUT
V+ LOGIC INPUT ON OFF 0V Q = DVOUT x CL LOGIC INPUT ON VG GND IN CL
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V+
C
V+ LOGIC INPUT 0V VNX
NO
COM
NC
VOUT RL 50 CL 35pF
IN SWITCH OUTPUT VOUT 90% 0V tD LOGIC INPUT GND
CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3. BREAK-BEFORE-MAKE TIME FIGURE 3B. TEST CIRCUIT
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ISL84467 Test Circuits and Waveforms (Continued)
V+ C SIGNAL GENERATOR rON = V1/100mA
NO or NC NO or NC
V+ C
VNX IN 0V or V+ 100mA V1 IN 0V or V+
ANALYZER RL
COM
COM
GND
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+ C V+ C SIGNAL GENERATOR
NO or NC COM
50
NO or NC
IN1 0V or V+ IMPEDANCE ANALYZER
COM NC or NO COM
IN
0V or V+
ANALYZER RL
GND
NC
GND
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL84467 is a bidirectional, quad single pole/double throw (SPDT) analog switch that offers precise switching capability from a single 1.65V to 4.5V supply with low ON-resistance (0.39) and high speed operation (tON = 33ns, tOFF = 16ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.65V), low power consumption (6.3W max), low leakage currents (165nA max), and the tiny TQFN package. The ultra low ON-resistance and rON flatness provide very low insertion loss and distortion to applications that require signal reproduction.
turn ON, creating a low impedance path from the V+ power supply to ground. This will result in a significant amount of current flow in the IC which can potentially create a latch-up state or permanently damage the IC. The external V+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. Under normal operation, the sub-microamp IDD current of the IC produces an insignificant voltage drop across the 100 series resistor resulting in no impact to switch operation or performance.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil recommends adding a 100 resistor in series with the V+ power supply pin of the ISL84467 IC (see Figure 8). During an overvoltage transient event, such as occurs during system level IEC 61000 ESD testing, substrate currents can be generated in the IC that can trigger parasitic SCR structures to
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ISL84467
. .
V+ OPTIONAL PROTECTION RESISTOR
NOx
C
OPTIONAL SCHOTTKY DIODE V+ OPTIONAL PROTECTION RESISTOR COMx
100
INX VNX VCOM
NCx
INx GND OPTIONAL SCHOTTKY DIODE GND
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND LATCH-UP IMMUNITY
FIGURE 9. OVERVOLTAGE PROTECTION
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 9). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provide additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 9). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Connecting schottky diodes to the signal pins (as shown in Figure 9) will shunt the fault current to the supply or to ground, thereby protecting the switch. These Schottky diodes must be sized to handle the expected fault current.
Power-Supply Considerations
The ISL84467 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4.7V maximum supply voltage, the ISL84467 5.5V maximum supply voltage provides plenty of room for the 10% tolerance of 4.3V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the "Electrical Specifications" tables starting on page 3 and the "Typical Performance Curves" starting on page 9 for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 3.0V to 4.5V (see Figure 19). At 3.0V the VIL level is about 0.53V. This is still above the 1.8V CMOS guaranteed low output maximum level of 0.5V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL84467 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example, driving the device with 2.85V logic (0V to 2.85V) while operating with a 4.2V supply the device draws only 12A of current (see Figure 17 for VIN = 2.85V).
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High-Frequency Performance
In 50 systems, the ISL84467 has a -3dB bandwidth of 104MHz (see Figure 22). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to its output. Off isolation is the resistance to this feedthrough, while crosstalk indicates the amount of feedthrough from one switch to another. Figure 23 details the high off isolation and crosstalk rejection provided by this part. At 100kHz, off isolation is about 65dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analog signal path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
Typical Performance Curves TA = +25C, unless otherwise specified
0.40 ICOM = 100mA 0.39 0.38 0.43 0.37 rON () rON () 0.36 0.35 0.34 0.33 0.32 0 1 2 VCOM (V) V+ = 3.9V V+ = 4.3V 0.37 V+ = 4.5V 3 4 5 0.36 0 0.5 1.0 1.5 2.0 VCOM (V) 2.5 3.0 3.5 0.42 0.41 0.40 0.39 0.38 V+ = 3V V+ = 2.7V 0.46 0.45 0.44 ICOM = 100mA
V+ = 3.3V
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.8 ICOM = 100mA V+ = 1.65V 0.7 V+ = 1.8V rON () 0.6 V+ = 2V 0.5
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
0.45 V+ = 4.3V ICOM = 100mA 0.40 +85C rON () 0.35 +25C
0.30 -40C
0.4 0 0.5 1.0 VCOM (V) 1.5 2.0
0.25 0 1 2 VCOM (V) 3 4 5
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
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ISL84467 Typical Performance Curves TA = +25C, unless otherwise specified (Continued)
0.50 V+ = 3.3V ICOM = 100mA 0.45 +85C +85C rON () 0.40 +25C 0.35 0.35 -40C 0.30 0 0.5 1.0 1.5 2.0 VCOM (V) 2.5 3.0 3.5 rON () 0.45 +25C 0.40 -40C 0.55 V+ = 2.7V ICOM = 100mA 0.50
0.30 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
0.70 +85C 0.65 0.60 0.55 0.50 0.45 +25C -40C
V+ = 1.8V ICOM = 100mA
200 V+ = 4.2V SWEEPING BOTH LOGIC INPUTS 150
rON ()
ION (mA) 0 0.5 1.0 VCOM (V) 1.5 2.o
100
50 0.40 0.35
0 0 1 2 3 VIN1, VIN 2 (V) 4 5
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 17. SUPPLY CURRENT vs VLOGIC VOLTAGE
250 200 150 VINH AND VINL (V) 100 50 V+ = 4.3V 0 V+ = 1.8V -50 -100 V+ = 3V
1.0 0.9 0.8 VINH 0.7 0.6 0.5 0.4 0.3 0.2 1.5
Q (pC)
VINL
0
1
2 VCOM (V)
3
4
5
2.0
2.5
3.0 V+ (V)
3.5
4.0
4.5
FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
10
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ISL84467 Typical Performance Curves TA = +25C, unless otherwise specified (Continued)
250 40 35 30 tOFF (ns) tON (ns) 150 25 +85C 20 50 +85C -40C 0 1.0 1.5 2.0 2.5 3.0 V+ (V) 3.5 4.0 4.5 10 1.0 1.5 2.0 2.5 3.0 V+ (V) 3.5 4.0 4.5 +25C 15 -40C +25C
200
100
FIGURE 20. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 21. TURN-OFF TIME vs SUPPLY VOLTAGE
-10 NORMALIZED GAIN (dB) V+ = 4.3V V+ = 3V 0 -20 GAIN -20 -30 -40 CROSSTALK (dB) -50 ISOLATION -60 -70 -80 CROSSTALK -90 -100 -110 1k
10 20 30 OFF ISOLATION (dB) 40 50 60 70 80 90 100 110 100M 500M
PHASE
0 20 40 60 80 PHASE ()
RL = 50 VIN = 0.2VP-P to 2VP-P 1M 10M FREQUENCY (Hz) 100M
100 600M
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 22. FREQUENCY RESPONSE
FIGURE 23. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT: 228 PROCESS: Si Gate CMOS
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ISL84467 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP)
2X A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X 0 TOP VIEW A2 A / / 0.10 C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 B E/2 E 2X 0.15 C B D D/2 0.15 C A
L16.3x3A
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e 1.35 1.35 0.18 MIN 0.70 NOMINAL 0.75 0.20 REF 0.23 3.00 BSC 2.75 BSC 1.50 3.00 BSC 2.75 BSC 1.50 0.50 BSC 0.20 0.30 0.40 16 4 4 0.60 12 0.50 1.65 1.65 0.30 MAX 0.80 0.05 0.80 NOTES 9 9 5, 8 9 7, 8, 10 9 7, 8, 10 8 2 3 3 9 9 Rev. 0 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
C
9
k L N Nd Ne P
9 CORNER OPTION 4X
SECTION "C-C" C L C L
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
L1 e 10 L
L1 CC e
10
L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension.
TERMINAL TIP FOR EVEN TERMINAL/SIDE
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN6521.0 July 17, 2007

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